Dr. Gary W. Rubloff
Research Topics
Process diagnostics, sensing, metrology, and control
Semiconductor manufacturing processes and equipment
Systems modeling, simulation, and optimization
Engineered learning systems

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Fall 2000: Evolution of Copper Interconnect









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Problem statement
The instructor identified a specific problem area for the course design project, that of the evolution of copper interconnect technology and integration in the semiconductor industry.  The industry is undergoing a paradigm shift in interconnect technology copper-based metallurgy and low dielectric constant (low-K) materials as insulators, because copper (Cu) lowers the resistance of the wires and low-K dielectrics reduce the capacitance of the wires.  

The realities of these materials and process changes force other major changes in manufacturing.  First, the processes change dramatically.  For Cu-based metallurgy, this forces an emphasis on Cu electroplating, Cu chemical vapor deposition (CVD), and CVD of ultrathin barrier layers.  For low-K dielectrics, both spin-on wet chemical deposition and enhanced CVD are important candidates, with major challenges in their extendibility to increasingly lower K values, materials stability, and reliability.  Second, the new processes require development of new approaches to manufacturing equipment design, incorporating not only multichamber (multi-reactor) "cluster tools", but also fundamental advances in reactor design.  Third, the limitation of dry etch processes for Cu metallurgy has demanded a new strategy for process integration, namely Damascene processing, with profound consequences on equipment design and integration.  Implementing these profound changes in materials, processes, equipment, and integration has been a major focus of the National and International Technology Roadmap for Semiconductors.

With this backdrop, the instructor focused the technology domain of the course on key aspects of how the Cu Interconnect Revolution will evolve, not only in terms of the technology but primarily the systems-level aspects which determine the evolution.  The focal point became the transition from first-generation metallization strategy, including physical vapor deposition (PVD) of the barrier layer and Cu electroplating, to the expected all-CVD combination, including CVD of both barrier layer and Cu fill.  Much of the industry expects this transition to occur ultimately, but time scales and details are unclear.  However, it is clear that technology, manufacturing cost, and manufacturing efficiency will all steer the evolution of the Cu interconnect era.

The project emphasized materials and processes, equipment design and logistics, factory-level logistics, and cost-of-ownership considerations, as well as the overall development of the project itself.  Each of these topics was the responsibility of a team in the class.  It was intended that the profound impact of this problem on semiconductor technology and its relevance to research interests at the University of Maryland would enhance the realism and meaning of the course experience for both systems and materials students.

Project teams were expected to meet regularly, outside of class as well as in class, to pursue their responsibilities. Team update presentations were given to the entire class several times through the course. Part of the class time, particularly earlier in the course, was devoted to lectures aimed at conveying key technology concepts and the relevance of systems engineering, particularly to that technology. The rest of class time was devoted to team meetings, with the instructor circulating between them, and to full-class discussions on the entire project, moderated by the instructor.

Primary course deliverables were:
Final presentation, structured as an executive overview
Final report, prepared as a Word document

Both are available at this site.

A final exam concentrating on the key issues of the project was given as a take-home individual exercise. Grading was 40% team project, 40% individual contributions to project and class participation, and 20% final exam.